CY28346 Datasheet, PDF (7/20 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

3.3V signals
tDC
-
3.3V
Output under Test
Probe
Load Cap
CY28346
-
2.4V
1.5V
0.4V
0V
Tr
Tf
Figure 3. For Single-ended Output Signals
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
VDD3 (3.3V +/- 5%)
1. Output impedance of the current mode buffer circuit – Ro
(see Figure 4).
2. Minimum and maximum required voltage operation range
of the circuit – Vop (see Figure 4).
3. Series resistance in the buffer circuit – Ros (see Figure 4).
4. Current accuracy at given configuration into nominal test
load for given configuration.
Ro
Iout
Ros
0V
Iout
Vout = 1.2V max
Figure 4. Buffer Characteristics
Table 4. Host Clock (HCSL) Buffer Characteristics
Characteristic
Ro
Ros
Vout
Min.
3000Ω (recommended)
N/A
Document #: 38-07331 Rev. *B
Slope ~ 1/R₀
1.2V
Vout
Max.
N/A
1.2V
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