CY28330 Datasheet, PDF (7/15 Pages) SpectraLinear Inc – Clock Generator for AMD™ Hammer

CY28330
Byte 7: Watchdog Control Register
Bit @Pup
Name
Description
7
0
Pin 12 Mode SRESET#; 1 = Pin 12 is the input pin which functions as a PD# signal. 0 = Pin 12 is the
Select
output pin as SRESET# signal.
6
0
Frequency This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog
Reversion time out only.
0 = selects frequency of existing H/W setting
1 = selects frequency of the second to last S/W setting. (the software setting prior to the
one that caused a system reboot).
5
0
For Test, ALWAYS program to ‘0’
4
0
WD Time-out This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears
the WD time stamps (WD3:0).
3
0
WD3
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
2
0
WD2
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9
1
0
0
0
WD1
WD0
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
Table 9. Watchdog Time Stamp
WD3
WD2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
WD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Off
1 second
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
Byte 8: Dial-a-Frequency™ Control Register N
Bit
@PUp
Description
7
0
ATPG Pulse. A 0 to 1 transition on this bit will trigger a differential pulse on the CPUT/C
lines whose pulse width is equal to the period of the currently latched frequency.
6
N6
These bits are for programming the PLL’s internal N register. This access allows the
5
N5
user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks
that are generated from the same PLL, such as PCI, remain at their existing ratios relative
4
N4
to the CPU clock.
3
N3
2
N2
1
N1
0
N0
Document #: 38-07366 Rev. *B
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