CY28317-2 Datasheet, PDF (7/21 Pages) Cypress Semiconductor – FTG for Mobile VIA PL133T and PLE133T Chipsets

Byte 3: Control Register 3
Bit
Pin#
Bit 7
–
Bit 6
–
Bit 5
27
Bit 4
26
Bit 3
Bit 2
Bit 1
–
31, 30
34, 33
Bit 0
37, 36
Byte 4: Control Register 4
Bit
Pin#
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
–
Bit 3
–
Bit 2
–
Bit 1
–
Bit 0
–
Byte 5: Control Register 5
Bit
Pin#
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
–
Bit 3
–
Bit 2
–
Bit 1
2
Bit 0
3
CY28317-2
Name
Reserved
SEL_48MHz
48MHz
24_48MHz
Reserved
SDRAM4:5
SDRAM2:3
SDRAM0:1
Default
1
0
1
1
1
1
1
1
Reserved
0 = 24 MHz
1 = 48 MHz
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Name
Reserved
Reserved
Reserved
CPU1
Stop Control
CPU0
Stop Control
CPUT and
CPUC Stop
Control
REF1
REF0
Default
0
0
0
0
0
0
1
1
Description
Reserved
Reserved
Reserved
0 = CPU1 will be stopped when
CPU_STOP# is active
1 = CPU1 will NOT be stopped when
CPU_STOP# is active
0 = CPU0 will be stopped when CPU_STOP# is active
1 = CPU0 will NOT be stopped when CPU_STOP# is
active
0 = CPUT and CPUC will be stopped when
CPU_STOP# is active
1 = CPUT and CPUC will NOT be stopped when
CPU_STOP# is active
(Active/Inactive)
(Active/Inactive)
Document #: 38-07094 Rev. *B
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