CY25823_11 Datasheet, PDF (7/15 Pages) Cypress Semiconductor – CK-SSCD Spread Spectrum Differential Clock Specification

CY25823
Byte 6: Vendor/Revision ID Register
Bit
@Pup
4
0
3
1
2
0
1
0
0
0
Pin#
–
–
–
–
–
Name
–
–
–
–
–
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Pin Description
Spread Enable and Spread Select[3:0]
PWRDWN (Power-down) Clarification
Spread Enable and Spread Select[3:0] register bits are used to
enable and disable spread spectrum on CLKOUT and to change
the spread modulation. When the spread selection changes, the
CLKOUT output transits to the target spread selection without
deviating from clock specifications.
At device power-up spread spectrum is enabled and hardware
control mode is enabled. The initial spread-spectrum configu-
ration is determined by the S[3:1] pins, which correspond to the
S[3:1] bits in Table 4. The S0 configuration bit is hard-coded to
zero when hardware control mode is selected. All four spread
spectrum configuration bits, S[3:0], can also be set when the
device is in the software control mode.
Charge Pump Select Byte1 [1:0]
Programming these bits (Byte1[1:0]) via I²C enables the user to
have more spread percentage options as described in Table 5.
At the start up the default value for byte1[1:0] bits is set to ‘00’,
this value can be changed via I²C to have higher spread
percentage on CLKOUT and CLKOUT#. Setting the byte[1:0]
bits to ‘11’ allows the user to have a slightly higher spread
percentage than the default value(00). The ‘01’ option is the
highest spread option for maximum EMI reduction.
The PWRDWN (Power-down) pin is used to shut off the clock
prior to shutting off power to the device. PWRDWN is an
asynchronous active HIGH input. This signal is synchronized
internally to the device powering down the clock synthesizer.
PWRDWN also is an asynchronous function for powering up the
system. When PWRDWN is high, all clocks are tri-stated and the
oscillator and PLL are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the stopped state. The CLKIN input must
be on and within specified operating parameters before
PWRDWN is asserted and it must remain in this state while
PWRDWN is asserted, see Figure 2.
When PWRDWN is de-asserted (CLKIN starts after powerdown
de-assertion to meet the IDD≤250μA specification) the clocks
should remain stopped until the VCO is stable and within speci-
fication (t_STABLE)., see Figure 3.
Figure 2. Power-down Assertion
PW RDW N
C LK IN
C lock V C O
CLKOUT
CLKOUT#
On
O ff
TpHZ
REFOUT
Document Number: 38-07579 Rev. *D
Page 7 of 15
[+] Feedback