CY24942 Datasheet, PDF (7/19 Pages) Cypress Semiconductor – 25 MHz Crystal or Clock Input

CY24292
Table 9. Byte 5: Control Register
Bit Type At Power up
Outputs Affected
7
R
0
Not applicable
6
R
0
Not applicable
5
R
0
Not applicable
4
R
1
Not applicable
3
R
1
Not applicable
2
R
0
Not applicable
1
R
0
Not applicable
0
R
0
Not applicable
Description
Revision ID bit 3
Revision ID bit 2
Revision ID bit 1
Revision ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Notes
Table 10. Byte 6: Control Register
Bit Type At Power up
Outputs Affected
0 to 7 R
Undefined Not applicable
Not used
Description
Notes
The state of the clock outputs upon assertion of the PD_RESET# signal from input pin or Global OE control bit from byte 0, bit 5 of
the SMBus is shown in the following table.
Table 11. Power Down Reset Table
H/W PD_RESET# (pin 24) S/W PD_RESET# (Byte 0 bit 5)
0
0
0
1
1
0
1
1
All Clock Outputs
Disabled, Hi-Z. 25M has weak pull-down.
Disabled, Hi-Z. 25M has weak pull-down.
Disabled, Hi-Z. 25M has weak pull-down.
Enabled
Document Number: 001-46142 Rev. *E
Page 7 of 19