CY24242 Datasheet, PDF (7/10 Pages) Cypress Semiconductor – Laser Printer System Frequency Synthesizer

CY24242
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DD = V_DDQ3 = 2.5V ± 5%, f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, V_DDC = 2.5V)
CPU = 66 MHz
CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15 – 15.5 10 – 10.5 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.2 – – 3.0 – – ns
t_L
Low Time
Duration of clock cycle below 0.4V
5 – – 2.8 – – ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
0.4 – 3.2 0.4 – 3.2 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
0.4 – 3.2 0.4 – 3.2 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45 – 55 45 – 55 %
1.25V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
– – 250 – – 250 ps
Maximum difference of cycle time
between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.25V
– – 250 – – 250 ps
f_ST
Frequency Stabilization Assumes full supply voltage reached – – 3 – – 3 ms
from Power-up (cold within 1 ms from power-up. Short
start)
cycles exist prior to frequency stabili-
zation.
Z_o
AC Output Impedance Average value during switching
– 20 – – 20 – Ω
transition. Used for determining series
termination value.
SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, V_DDC = 2.5V)
CPU = 66 MHz
CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15 – 15.5 10 – 10.5 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.2 – – 3.0 –
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5 – – 2.8 –
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
0.4 – 3.2 0.4 – 3.2 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
0.4 – 3.2 0.4 – 3.2 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45 – 55 45 – 55 %
1.25V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
– – 250 – – 250 ps
Maximum difference of cycle time
between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.25V
– 250 300 – 250 350 ps
f_ST
Frequency Stabilization Assumes full supply voltage reached
– – 3 – – 3 ms
from Power-up (cold within 1 ms from power-up. Short cycles
start)
exist prior to frequency stabilization.
Z_o
AC Output Impedance Average value during switching
– 20 – – 20 – Ω
transition. Used for determining series
termination value.
Document #: 38-07268 Rev. *B
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