CY14C101Q Datasheet, PDF (7/34 Pages) Cypress Semiconductor – 1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data retention: 20 years at 85 °C

CY14C101Q
CY14B101Q, CY14E101Q
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X101Q has two separate pins for SI and SO, which can be
connected with the master as shown in Figure 4 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 1-Mbit serial nvSRAM requires a 3-byte address for any read
or write operation. However, since the address is only 17 bits, it
implies that the first seven bits which are fed in are ignored by
the device. Although these seven bits are ‘don’t care’, Cypress
recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X101Q uses the standard opcodes for memory accesses.
In addition to the memory accesses, it provides additional
opcodes for the nvSRAM specific functions: STORE, RECALL,
AutoStore Enable, and AutoStore Disable. Refer to Table 2 on
page 9 for details.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tri-stated.
Status Register
CY14X101Q has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 4 on page 10.
Figure 4. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
SCK SI
SO
C Y 1 4 X 1 01Q
SCK SI
SO
CY14X 101Q
CS1
HOLD1
CS2
HOLD2
CS
HOLD
CS
HOLD
SPI Modes
CY14X101Q may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■ SPI Mode 0 (CPOL=0, CPHA=0)
■ SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles, is considered. The output data
is available on the falling edge of SCK.
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in standby mode and not
transferring data is:
■ SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for either
Mode 0 or Mode 3. The device detects the SPI mode from the
status of SCK pin when the device is selected by bringing the CS
pin LOW. If SCK pin is LOW when the device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
Figure 5. SPI Mode 0
CS
SCK
012 345 67
SI
7 654321 0
MSB
LSB
Document #: 001-54393 Rev. *F
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