MB95F613H Datasheet, PDF (68/110 Pages) Cypress Semiconductor – F2MC-8FX CPU core

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MB95610H Series
15.8.3 Port G registers
■ Port G register functions
Register
abbreviation
Data
0
PDRG
1
0
DDRG
1
0
PULG
1
Read
Pin state is “L” level.
Pin state is “H” level.
Read by read-modify-write
(RMW) instruction
PDRG value is “0”.
PDRG value is “1”.
Port input enabled
Port output enabled
Pull-up disabled
Pull-up enabled
Write
As output port, outputs “L” level.
As output port, outputs “H” level.
■ Correspondence between registers and pins for port G
Correspondence between related register bits and pins
Pin name
-
-
-
-
-
PG2
PG1
-
PDRG
DDRG
-
-
-
-
-
bit2
bit1
-
PULG
15.8.4 Port G operations
■ Operation as an output port
❐ A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
❐ If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is.
❐ Reading the PDRG register returns the PDRG register value.
■ Operation as an input port
❐ A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
❐ For a pin shared with other peripheral functions, disable the output of such peripheral functions.
❐ If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port.
❐ Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the
PDRG register, the PDRG register value is returned.
■ Operation as a peripheral function input pin
❐ To set a pin as an input port, set the bit in the DDRG register corresponding to the input pin of a peripheral function to “0”.
❐ Reading the PDRG register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin.
However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned.
■ Operation at reset
If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.
■ Operation in stop mode and watch mode
❐ If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch
mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that
pin is locked to “L” level and blocked in order to prevent leaks due to input open.
❐ If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output
level is maintained.
■ Operation of the pull-up register
Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level,
the pull-up resistor is disconnected regardless of the value of the PULG register.
Document Number: 002-04698 Rev. *A
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