CY7C67300_13 Datasheet, PDF (65/112 Pages) Cypress Semiconductor – EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support

CY7C67300
HPI Status Port [] [HPI: R]
Table 103. HPI Status Port
Bit #
15
14
Field
VBUS
ID
Flag
Flag
Read/Write
R
R
Default
X
X
13
Reserved
-
X
12
SOF/EOP2
Flag
R
X
11
Reserved
-
X
10
SOF/EOP1
Flag
R
X
9
Reset2
Flag
R
X
8
Mailbox In
Flag
R
X
Bit #
Field
Read/Write
Default
7
Resume2
Flag
R
X
6
Resume1
Flag
R
X
5
SIE2msg
R
X
4
SIE1msg
R
X
3
Done2
Flag
R
X
2
Done1
Flag
R
X
1
Reset1
Flag
R
X
0
Mailbox Out
Flag
R
X
Register Description
The HPI Status Port provides the external host processor with
the MailBox status bits plus several SIE status bits. This register
is not accessible from the on-chip CPU. The additional SIE status
bits are provided to aid external device driver firmware devel-
opment, and are not recommended for applications that do not
have an intimate relationship with the on-chip BIOS.
Reading from the HPI Status Port does not result in a CPU HPI
interface memory access cycle. The external host may continu-
ously poll this register without degrading the CPU or DMA perfor-
mance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read only bit that indicates whether OTG
VBus is greater than 4.4V. After turning on VBUS, firmware must
wait at least 10 µs before this reading this bit.
1: OTG VBus is greater than 4.4V
0: OTG VBus is less than 4.4V
ID Flag (Bit 14)
The ID Flag bit is a read only bit that indicates the state of the
OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read only bit that indicates if a
message is ready in the incoming mailbox. This interrupt clears
when the on-chip CPU reads from the HPI Mailbox register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read only bit that indicates if a USB
resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read only bit that indicates if a USB
resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU wrote to the SIE2msg register. This bit is
cleared on an HPI read.
1: The SIE2msg register was written by the CY7C67300 CPU
0: The SIE2msg register was not written by the CY7C67300 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU wrote to the SIE1msg register. This bit is
cleared on an HPI read.
1: The SIE1msg register was written by the CY7C67300 CPU
0: The SIE1msg register was not written by the CY7C67300 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read only bit that indicates
if a host packet done interrupt occurs on Host 2. In device mode
this read only bit indicates if an any of the endpoint interrupts
occur on Device 2. Firmware needs to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Document Number: 38-08015 Rev. *L
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