W166 Datasheet, PDF (6/7 Pages) Cypress Semiconductor – Spread Spectrum Frequency Timing Generator

W166
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V_DD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V_DD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended a 2-layer board layout.
Reference Input
1
NC ₂
GND ₃
4
8
R1
7
6
VDD
5
Clock Output
C1
0.1 µF
3.3 or 5V System Supply
FB
C2
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
Reference Input
NC
G
C1 =
C2 =
R1 =
High frequency supply decoupling
capacitor (0.1 µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
Match value to line impedance
FB = ^{Ferrite Bead}
G = Via To GND Plane
R1
Clock Output
C1
G
C2
G
Power Supply Input
FB
(3.3V or 5V)
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
Package
Name
W166
G
Package Type
8-pin Plastic SOIC (150-mil)
Document: #38-00878
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