FM25V02A Datasheet, PDF (6/23 Pages) Cypress Semiconductor – 256-Kbit (32K × 8) Serial (SPI) F-RAM

FM25V02A
The device detects the SPI mode from the status of the SCK pin
when the device is selected by bringing the CS pin LOW. If the
SCK pin is LOW when the device is selected, SPI Mode 0 is
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.
Figure 5. SPI Mode 0
CS
SCK
0 1 234 56 7
SI
7 6543210
MSB
LSB
Figure 6. SPI Mode 3
CS
SCK
0 1 234 56 7
SI
7 654321 0
MSB
LSB
Power-Up to First Access
The FM25V02A is not accessible for a t_PU time after power-up.
Users must comply with the timing parameter t_PU, which is the
minimum time from V_DD (min) to the first CS LOW.
Command Structure
There are nine commands, called opcodes, that can be issued
by the bus master to the FM25V02A. They are listed in Table 1.
These opcodes control the functions performed by the memory.
Table 1. Opcode Commands
Name
WREN
WRDI
RDSR
WRSR
READ
FSTRD
WRITE
SLEEP
RDID
Reserved
Description
Set write enable latch
Reset write enable latch
Read Status Register
Write Status Register
Read memory data
Fast read memory data
Write memory data
Enter sleep mode
Read device ID
Reserved
Opcode
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 0011b
0000 1011b
0000 0010b
1011 1001b
1001 1111b
1100 0011b
1100 0010b
0101 1010b
0101 1011b
WREN - Set Write Enable Latch
The FM25V02A will power up with writes disabled. The WREN
command must be issued before any write operation. Sending
the WREN opcode allows the user to issue subsequent opcodes
for write operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN opcode causes the internal Write Enable
Latch to be set. A flag bit in the Status Register, called WEL,
indicates the state of the latch. WEL = ‘1’ indicates that writes are
permitted. Attempting to write the WEL bit in the Status Register
has no effect on the state of this bit - only the WREN opcode can
set this bit. The WEL bit will be automatically cleared on the rising
edge of CS following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or the F-RAM
array without another WREN command. Figure 7 illustrates the
WREN command bus configuration.
Figure 7. WREN Bus Configuration
CS
SCK
01 234567
SI
00000110
SO
HI-Z
WRDI - Reset Write Enable Latch
The WRDI command disables all write activity by clearing the
Write Enable Latch. The user can verify that writes are disabled
by reading the WEL bit in the Status Register and verifying that
WEL is equal to ‘0’. Figure 8 illustrates the WRDI command bus
configuration.
Figure 8. WRDI Bus Configuration
CS
SCK
01 234567
SI
0000 0 10 0
SO
HI-Z
Document Number: 001-90865 Rev. *F
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