CY7C68013A_08 Datasheet, PDF (6/62 Pages) Cypress Semiconductor – EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
1
2
3
4
5
6
INT4VEC Value
80
84
88
8C
90
94
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
7
98
EP6EF
8
9C
EP8EF
9
A0
EP2FF
10
A4
EP4FF
11
A8
EP6FF
12
AC
EP8FF
13
B0
GPIFDONE
14
B4
GPIFWF
Notes
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
Endpoint 4 Full Flag
Endpoint 6 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the FX 2LP substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX2LP
pushes the program counter onto its stack then jumps to address
0x0053, where it expects to find a “jump” instruction to the ISR
Interrupt service routine.
3.9 Reset and Wakeup
3.9.1 Reset Pin
The input pin, RESET#, resets the FX2LP when asserted. This
pin has hysteresis and is active LOW. When a crystal is used with
the CY7C680xxA the reset period must allow for the stabilization
of the crystal and the PLL. This reset period must be approxi-
mately 5 ms after VCC reaches 3.0V. If the crystal input pin is
driven by a clock signal the internal PLL stabilizes in 200 μs after
VCC has reached 3.0V.^[3]
Figure 2 on page 7 shows a power on reset condition and a reset
applied during operation. A power on reset is defined as the time
reset that is asserted while power is being applied to the circuit.
A powered reset is when the FX2LP powered on and operating
and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation. For more infor-
mation about reset implementation for the FX2 family of products
visit http://www.cypress.com.
Note
3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.
Document #: 38-08032 Rev. *L
Page 6 of 62
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