CY7C4205 Datasheet, PDF (6/25 Pages) Cypress Semiconductor – 64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

CY7C4425/4205/4215
CY7C4225/4235/4245
Switching Characteristics Over the Operating Range (continued)
Parameter
t_PAFsynch
t_PAEasynch
t_PAEsynch
t_HF
t_XO
t_XI
t_XIS
t_SKEW1
t_SKEW2
t_SKEW3
Description
Clock to Programmable Almost-Full Flag
(Synchronous mode, V_CC/SMODE tied to V_SS)
Clock to Programmable Almost-Empty Flag^[12]
(Asynchronous mode, V_CC/SMODE tied to V_CC)
Clock to Programmable Almost-Full Flag
(Synchronous mode, V_CC/SMODE tied to V_SS)
Clock to Half-Full Flag
Clock to Expansion Out
Expansion in Pulse Width
Expansion in Set-Up Time
Skew Time between Read Clock and Write
Clock for Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Pro-
grammable Almost Full Flags.
7C42X5-10
Min. Max.
8
12
8
12
7
3
4.5
5
5
10
7C42X5-15
Min. Max.
10
16
10
16
10
6.5
5
6
6
15
7C42X5-25
Min. Max.
15
20
15
20
15
10
10
10
10
18
7C42X5-35
Min. Max.
20
25
20
25
20
14
15
12
12
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Write Cycle Timing
t_CLKH
t_CLK
t_CLKL
WCLK
D₀ –D₁₇
WEN
FF
t_WFF
t_DS
t_ENS
t_DH
t_ENH
t_WFF
NO OPERATION
RCLK
t_SKEW1[13]
REN
42X5–6
Notes:
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
12. _PAFasynch, t_PAEasynch, after program register write will not be valid until 5 ns + t_PAF(E).
13. t_SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t_SKEW1, then FF may not change state until the next WCLK edge.
6