CY7C343B Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 64-Macrocell MAX EPLD

CY7C343B
External Asynchronous Switching Characteristics Over Operating Range
Parameter
Description
t_ACO1
Asynchronous Clock Input to Output
Delay^[3]
t_AS1
Dedicated Input or Feedback Set-Up
Time to Asynchronous Clock Input
t_AH
Input Hold Time from Asynchronous
Clock Input
t_AWH
Asynchronous Clock Input HIGH
Time^[6]
t_AWL
Asynchronous Clock Input LOW
Time^[6]
t_ACNT
Minimum Internal Array Clock
Frequency
f_ACNT
Maximum Internal Array Clock
Frequency^[5]
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
7C343B-25
Min. Max.
25
7C343B-30
Min. Max.
30
5
6
6
8
11
14
9
11
20
25
50
40
7C343B-35
Min. Max.
35
8
10
16
14
30
33.3
Unit
ns
ns
ns
ns
ns
ns
MHz
Internal Switching Characteristics Over Operating Range
7C343B-25
7C343B-30
7C343B-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
t_IN
Dedicated Input Pad and Buffer Delay Com’l/Ind
5
7
11
ns
t_IO
I/O Input Pad and Buffer Delay
Com’l/Ind
6
6
11
ns
t_EXP
Expander Array Delay
Com’l/Ind
12
14
20
ns
t_LAD
Logic Array Data Delay
Com’l/Ind
12
14
14
ns
t_LAC
Logic Array Control Delay
Com’l/Ind
10
12
13
ns
t_OD
Output Buffer and Pad Delay^[3]
Com’l/Ind
5
5
6
ns
t_ZX
Output Buffer Enable Delay^[3]
Com’l/Ind
10
11
13
ns
t_XZ
Output Buffer Disable Delay^[7]
Com’l/Ind
10
11
13
ns
t_RSU
Register Set-Up Time Relative to
Com’l/Ind
6
Clock Signal at Register
8
12
ns
t_RH
Register Hold Time Relative to Clock Com’l/Ind
4
6
8
ns
Signal at Register
t_LATCH
Flow-Through Latch Delay
Com’l/Ind
3
4
4
ns
t_RD
Register Delay
Com’l/Ind
1
2
2
ns
t_COMB
Transparent Mode Delay
Com’l/Ind
3
4
4
ns
t_IC
Asynchronous Clock Logic Delay
Com’l/Ind
14
16
18
ns
t_ICS
Synchronous Clock Delay
Com’l/Ind
3
2
1
ns
t_FD
Feedback Delay
Com’l/Ind
1
1
2
ns
t_PRE
Asynchronous Register Preset Time Com’l/Ind
5
6
7
ns
t_CLR
Asynchronous Register Clear Time Com’l/Ind
5
6
7
ns
t_PIA
Programmable Interconnect Array
Com’l/Ind
14
16
20
ns
Delay Time
Notes:
6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the t_ACH and t_ACL parameter must be swapped.
7. C1 = 5 pF.
Document #: 38-03038 Rev. **
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