CY7C341B Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 192-Macrocell MAX EPLD

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CY7C341B
External Switching Characteristics Over the Operating Range
Parameter
Description
t_PD1
Dedicated Input to Combinatorial Output Delay^[4]
Commercial
t_PD2
I/O Input to Combinatorial Output Delay^[4]
Commercial
t_SU
Global Clock Set-up Time
t_CO1
Synchronous Clock Input to Output Delay^[4]
Commercial
Commercial
t_H
Input Hold Time from Synchronous Clock Input
Commercial
t_WH
Synchronous Clock Input High Time
Commercial
t_WL
f_MAX
t_ACO1
Synchronous Clock Input Low Time
Commercial
Maximum Register Toggle Frequency^[5]
Commercial
Dedicated Asynchronous Clock Input to Output Delay^[4] Commercial
t_AS1
Dedicated Input or Feedback Set-up Time to
Asynchronous Clock Input
Commercial
t_AH
t_AWH
t_AWL
t_CNT
t_ODH
f_CNT
t_ACNT
f_ACNT
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time^[6]
Asynchronous Clock Input LOW Time^[6]
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency^[7]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency^[7]
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
7C341B-25
Min. Max.
25
40
15
14
0
8
8
62.5
25
5
6
11
9
20
2
50
20
50
7C341B-35
Min. Max.
35
55
25
20
0
12.5
12.5
40.0
35
10
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
10
ns
16
ns
14
ns
30 ns
2
ns
33.3
MHz
30 ns
33.3
MHz
Internal Switching Characteristics Over the Operating Range
7C341B-25
7C341B-35
Parameter
Description
Min. Max Min. Max Unit
t_IN
Dedicated Input Pad and Buffer Delay Commercial
t_IO
I/O Input Pad and Buffer Delay
Commercial
t_EXP
Expander Array Delay
Commercial
t_LAD
Logic Array Data Delay
Commercial
t_LAC
Logic Array Control Delay
t_OD
Output Buffer and Pad Delay^[4]
t_ZX
Output Buffer Enable Delay^[4]
t_XZ
Output Buffer Disable Delay^[8]
Commercial
Commercial
Commercial
Commercial
t_RSU
Register Set-Up Time Relative to Clock Commercial
Signal at Register
5
11
ns
6
11
ns
12
20
ns
12
14
ns
10
13
ns
5
6
ns
10
13
ns
10
13
ns
6
12
ns
t_RH
Register Hold Time Relative to Clock Commercial
4
Signal at Register
8
ns
t_LATCH
Flow-Through Latch Delay
Commercial
3
4
ns
t_RD
Register Delay
Commercial
1
2
ns
t_COMB
Transparent Mode Delay
Commercial
3
4
ns
t_IC
Asynchronous Clock Logic Delay
Commercial
14
16
ns
t_ICS
Synchronous Clock Delay
Commercial
3
1
ns
Notes:
4. C1 = 35 pF.
5. The f_MAX values represent the highest frequency for pipeline data.
6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the t_ACH and t_ACL parameter must be swapped.
7. This parameter is measured with a 16-bit counter programmed into each LAB.
8. C1 = 5 pF.
Document #: 38-03016 Rev. *C
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