CY7C25682KV18 Datasheet, PDF (6/29 Pages) Cypress Semiconductor – 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C25682KV18
CY7C25702KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
ZQ
Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q_[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V_DDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
Input
PLL Turn Off  Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in
DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with DDR I timing.
TDO
Output TDO Pin for JTAG.
TCK
Input TCK Pin for JTAG.
TDI
Input TDI Pin for JTAG.
TMS
Input TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
Input Not Connected to the Die. Can be tied to any voltage level.
NC/288M
Input Not Connected to the Die. Can be tied to any voltage level.
V_REF
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
Reference measurement points.
V_DD
V_SS
V_DDQ
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-66483 Rev. *B
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