CY7C1380CV25 Datasheet, PDF (6/33 Pages) Cypress Semiconductor – 512K x 36/1M x 18 Pipelined SRAM

PRELIMINARY
CY7C1380CV25
CY7C1382CV25
Pin Definitions
Name
A0
A1
A
BWa
BWb
BWc
BWd
GW
BWE
CLK
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
CE₁
Input-
Synchronous
CE₂
Input-
Synchronous
CE₃
Input-
Synchronous
OE
Input-
Asynchronous
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
ADSC
Input-
Synchronous
MODE
Input-Pin
ZZ
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
Input-
Asynchronous
I/O-
Synchronous
TDO
TDI
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Document #: 38-05240 Rev. *A
Description
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂,
and CE₃ are sampled active. A_[1:0] feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE₂ and CE₃ to select/deselect the device. ADSP is ig-
nored if CE₁ is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE₁ and CE₃ to select/deselect the device. (TQFP Only)
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE₁ and CE₂ to select/deselect the device. (TQFP Only)
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A_[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE₁ is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A_[x:0] is captured in the address registers. A_[1:0] are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to V_DDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time
critical “sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A_[X] during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition. DQ a,b,c, and d are 8 bits wide and the DP
a,b,c, and d are 1 bit wide.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. (BGA Only)
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.(BGA
Only)
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