CY7C1352 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 256K x18 Pipelined SRAM with NoBL Architecture

CY7C1352
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
Supply Voltage on V_DD Relative to GND .........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State^[7] .....................................−0.5V to V_DDQ + 0.5V
DC Input Voltage^[7]..................................−0.5V to V_DDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature^[8]
Com’l
0°C to +70°C
V_DD/V_DDQ
3.3V ± 5%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
V_DD
V_DDQ
V_OH
V_OL
V_IH
V_IL
I_X
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage^[7]
V_DD = Min., I_OH = -4.0 mA^[9]
V_DD = Min., I_OL = 8.0 mA^[9]
Input Load Current
GND ≤ V_I ≤ V_DDQ
Input Current of MODE
3.135 3.465
V
3.135 3.465
V
2.4
V
0.4
V
2.0 V_DD + 0.3V V
−0.3
0.8
V
−5
5
µA
−30
30
µA
I_OZ
Output Leakage
GND ≤ V_I ≤ V_DDQ, Output Disabled
Current
−5
5
µA
I_CC
V_DD Operating Supply V_DD = Max., I_OUT = 0 mA,
7.0-ns cycle, 143 MHz
f = f_MAX = 1/t_CYC
7.5-ns cycle, 133 MHz
450
mA
400
mA
10-ns cycle, 100 MHz
350
mA
12.5-ns cycle, 80 MHz
300
mA
I_SB1
Automatic CE
Max. V_DD, Device Deselected, 7.0-ns cycle, 143 MHz
Power-Down
Current—TTL Inputs
V_IN ≥ V_IH or V_IN ≤ V_IL
f = f_MAX = 1/t_CYC
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
70
mA
60
mA
50
mA
12.5-ns cycle, 80 MHz
40
mA
I_SB2
Automatic CE
Max. V_DD, Device Deselected, All speed grades
Power-Down
V_IN ≤ 0.3V or V_IN > V_DDQ – 0.3V,
Current—CMOS
f=0
Inputs
5
mA
I_SB3
Automatic CE
Max. V_DD, Device Deselected, or 7.0-ns cycle, 143 MHz
Power-Down
Current—CMOS
V_IN ≤ 0.3V or V_IN > V_DDQ – 0.3V
f = f_MAX = 1/t_CYC
7.5-ns cycle, 133 MHz
Inputs
10-ns cycle, 100 MHz
60
mA
50
mA
40
mA
12.5-ns cycle, 80 MHz
30
mA
Notes:
7. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
8. T_A is the case temperature.
9. The load used for V_OH and V_CL testing is shown in part (b) of A/C Test Loads and Waveforms.
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