CY7C1143KV18 Datasheet, PDF (6/29 Pages) Cypress Semiconductor – 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1143KV18, CY7C1145KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
TDI
Input TDI Pin for JTAG.
TMS
Input TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
V_REF
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
reference measurement points.
V_DD
V_SS
V_DDQ
Power supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-58910 Rev. *D
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