CY7B995_11 Datasheet, PDF (6/17 Pages) Cypress Semiconductor – 2.5/3.3 V 200-MHz High-Speed Multi-Phase PLL Clock Buffer

RoboClock^, CY7B995
Table 3. Feedback Divider Settings
DS[1:0]
LL
LM
LH
ML
MM
MH
HL
HM
HH
N-Feedback Input
Divider
2
3
4
5
1
6
8
10
12
Permitted Output Divider
Connected to FB
1 or 2
1
1,2 or 4
1 or 2
1,2 or 4
1 or 2
1 or 2
1
1
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
controlled by 3F[1:0] and 4F[1:0] as indicated in Table 4 and
Table 5, respectively.
Table 4. Output Divider Settings – Bank 3
3F[1:0]
LL
HH
Other^[5]
K - Bank3 Output Divider
2
4
1
Table 5. Output Divider Settings – Bank 4
4F[1:0]
LL
Other^[5]
M- Bank4 Output Divider
2
1
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in Table 6.
Table 6. Output Frequency Settings
Configuration
Output Frequency
FB Input
Connected to
12QQ[0[0:1:1] _]a[6n_]d
3Q[0:1]
4Q[0:1]
1Qn or 2Qn
3Qn
4Qn
(N / R) x F_REF (N / R) x (1 / (N / R) x (1 /
K) x F_REF
M) x F_REF
(N / R) x K x (N / R) x F_REF (N / R) x (K /
F_REF
M) x F_REF
(N / R) x M x (N / R) x (M / (N / R) x F_REF
F_REF
K) x F_REF
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that
corresponds to each FS level is given in Table 7.
Table 7. Frequency Range Select
FS
PLL Frequency Range
L
24 to 50 MHz
M
48 to 100 MHz
H
96 to 200 MHz
Selectable output skew is in discrete increments of time units
(t_U).The value of t_U is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the t_U value is: t_U = 1 / (f_NOM × MF)
where MF is a multiplication factor which is determined by the FS
setting as indicated in Table 8.
Table 8. MF Calculation
FS
MF
f_NOM at which t_U is 1.0 ns (MHz)
L
32
31.25
M
16
62.5
H
8
125
Table 9. Output Skew Settings
nF[1:0]
LL^[7]
LM
LH
ML
MM
MH
HL
HM
HH
Skew
(1Q[0:1],2Q[0:1])
–4t_U
–3t_U
–2t_U
–1t_U
Zero Skew
+1t_U
+2t_U
+3t_U
+4t_U
Skew
(3Q[0:1])
Divide By 2
–6t_U
–4t_U
–2t_U
Zero Skew
+2t_U
+4t_U
+6t_U
Divide By 4
Skew
(4Q[0:1])
Divide By 2
–6t_U
–4t_U
–2t_U
Zero Skew
+2t_U
+4t_U
+6t_U
Inverted^[8]
Notes
5. These states are used to program the phase of the respective banks. See Table 8 and Table 9.
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given
reference frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO
frequency, and is within the range specified by FS pin. See Table 7.
7. LL disables outputs if TEST = MID and sOE# = HIGH.
8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
Document Number: 38-07337 Rev. *F
Page 6 of 17
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