CY62167EV30_12 Datasheet, PDF (6/19 Pages) Cypress Semiconductor – 16-Mbit (1 M × 16 / 2 M × 8) Static RAM

CY62167EV30 MoBL^®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ ^[12] Max Unit
V_DR
V_CC for data retention
1.5 –
I_CCDR[13] Data retention current V_CC = 1.5 V to 3.0 V,
Industrial 48-pin TSOP I –
–
CE₁ > V_CC  0.2 V or CE₂ < 0.2 V or
(BHE and BLE) > V_CC – 0.2 V,
V_IN > V_CC  0.2 V or V_IN < 0.2 V
–V
8 A
t_CDR[14]
t_R[15]
V_CC = 1.5 V, CE₁ > V_CC  0.2 V or
CE₂ < 0.2 V or
Industrial
Other
–
packages
(BHE and BLE) > V_CC – 0.2 V, _{Automotive-A All packages –}
V_IN > V_CC  0.2 V or V_IN < 0.2 V
– 10 A
– 10 A
Chip deselect to data
retention time
0
–
––
Operation recovery
time
45 –
– ns
Data Retention Waveform
V_CC
CE₁ or
[16]
BHE.BLE
or
CE₂
Figure 4. Data Retention Waveform
V_CC(min)
t_CDR
DATA RETENTION MODE
V_DR > 1.5 V
V_CC(min)
t_R
Notes
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V_CC = V_CC(typ), T_A = 25 °C.
13. Chip enables (CE₁ and CE₂), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the I_SB1 / I_SB2 / I_CCDR spec. Other inputs can be left floating.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear V_CC ramp from V_DR to V_CC(min) > 100 s or stable at V_CC(min) > 100 s.
16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05446 Rev. *L
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