CY62136EV30_09 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

Switching Waveforms ^{[14, 15]}
Read Cycle 1 (Address Transition Controlled)^{[14, 15]}
t_RC
ADDRESS
DATA OUT
t_OHA
t_AA
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)^{[15, 16]}
CY62136EV30
MoBL^®
DATA VALID
ADDRESS
CE
OE
BHE/BLE
t_RC
t_ACE
t_DOE
t_LZOE
DATA OUT
V_CC
SUPPLY
CURRENT
t_DBE
t_LZBE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
Notes:
14. The device is continuously selected. OE, CE = V_IL, BHE and/or BLE = V_IL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
DATA VALID
t_PD
t_HZCE
t_HZOE
t_HZBE
HIGH
IMPEDANCE
I_CC
50%
I_SB
Document #: 38-05569 Rev. *B
Page 6 of 12
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