CY62128BN_10 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM

Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)^{[12, 13]}
CY62128BN
MoBL^
ADDRESS
t_RC
CE₁
CE₂
OE
DATA OUT
V_CC
SUPPLY
CURRENT
t_ACE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
DATA VALID
t_HZOE
t_HZCE
HIGH
IMPEDANCE
t_PD
I_CC
50%
I_SB
Write Cycle No. 1 (CE₁ or CE₂ Controlled)^{[14, 15]}
ADDRESS
CE₁
CE₂
WE
DATA I/O
t_SA
t_AW
t_WC
t_SCE
t_PWE
t_SCE
t_SD
DATA VALID
t_HA
t_HD
Notes:
13. Address valid prior to or coincident with CE₁ transition LOW and CE₂ transition HIGH.
14. Data I/O is high impedance if OE = V_IH.
15. If CE₁ goes HIGH or CE₂ goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06498 Rev. *B
Page 6 of 12
[+] Feedback