CY2XP41_11 Datasheet, PDF (6/10 Pages) Cypress Semiconductor – Crystal to LVPECL Clock Generator

Measurement Definitions
Figure 2. Output Load AC Test Circuit
3.3 V
CLK
CLK#
3.3 V
110Ω
Z=50Ω
110Ω
Z=50Ω
62Ω
62Ω ^2pF
Measurement
Point
2pF
CY2XP41
Noise Power
Figure 3. RMS Phase Jitter
Phase Noise
Phase Noise Mask
20 dB/Decade
40 dB/Decade
1.5 MHz
10 MHz
Offset Frequency
RMS Jitter = vArea Under the Masked Phase Noise Plot
CLK
CLK#
Figure 4. Output Duty Cycle
T_PERIOD
T_PW
T_DC =
T_PW
T_PERIOD
Figure 5. Output Rise and Fall Time and Peak-Peak Voltage Swing
CLK
80%
V_PP
20%
CLK#
T_R
VSS
T_F
V_CM
Document #: 001-48923 Rev. *C
Page 6 of 10
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