CY2DP3110 Datasheet, PDF (6/9 Pages) Cypress Semiconductor – 1 of 2:10 Differential Clock/Data Fanout Buffer

FastEdge™ Series
CY2DP3110
Test Configuration
Standard test load using a differential pulse generator and
differential measurement instrument.
VTT
P ulse
G enerator
Z = 50 ohm
RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
DUT
CY2DP3110
5"
Zo = 50 ohm
5"
VTT
Figure 5. CY2DP3110 AC Test Reference
VTT
RT = 50 ohm
RT = 50 ohm
VTT
Applications Information
Termination Examples
C Y 2D P 3110
VCC
VTT
RT = 50 ohm
5"
Zo = 50 ohm
5"
VTT
RT = 50 ohm
VEE
Figure 6. Standard LVPECL – PECL Output Termination
CY2DP3110
VCC
VTT
RT = 50 ohm
5"
Zo = 50 ohm
5"
VTT
RT = 50 ohm
VEE
V B B (3.3V )
Figure 7. Driving a PECL/ECL Single-ended Input
Document #: 38-07469 Rev.*G
Page 6 of 9