CY28323B Datasheet, PDF (6/22 Pages) Cypress Semiconductor – FTG for Intel Pentium 4 CPU and Chipsets

CY28323B
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
Description
1
Start
2:8 Slave address – 7 bits
9
Write
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
19
Acknowledge from slave
20:27 Data byte – 8 bits
28
Acknowledge from slave
29
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Data Byte Configuration Map
Data Byte 0
Bit
Bit 7
Bit 6
Bit 5
Pin#
--
--
--
Name
Spread Select2
Spread Select1
Spread Select0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-- SEL4
-- SEL3
-- SEL2
-- SEL1
-- SEL0
Description
‘000’ = OFF
‘001’ = Reserved
‘010’ = Reserved
‘011’ = Reserved
‘100’ = ±0.25%
‘101’ = –0.5%
‘110’ = ±0.5%
‘111’ = ±0.38%
SW Frequency selection bits. See Table 4.
Power On
Default
0
0
0
0
0
0
0
0
Data Byte 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Pin#
38, 37
41, 40
22
23
27
Name
CPU1, CPU1#
CPU0, CPU0#
48MHz
24_48MHz
3V66_3
Document #: 38-07453 Rev. *B
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Power On
Default
1
1
1
1
1
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