CY25568_11 Datasheet, PDF (6/14 Pages) Cypress Semiconductor – Spread Spectrum Clock Generator 4 to 32 MHz Input frequency range

CY25568
Spread % Selection
The CY25568 provides Center-Spread, Down-Spread and No-Spread functions. These functions and the amount of Spread% are
selected by using 3-Level S0 and S1 digital inputs and are given in Table 3.
Table 3. Spread% Selection
XIN
(MHz)
4-5
5-6
6-7
7-8
8-10
10-12
12-14
14-16
16-20
20-24
24-28
28-32
FRSEL
0
0
0
0
1
1
1
1
M
M
M
M
S1=0
S0=0
CENTER
(%)
+/–1.4
+/–1.3
+/–1.2
+/–1.1
+/–1.4
+/–1.3
+/–1.2
+/–1.1
+/–1.4
+/–1.3
+/–1.2
+/–1.1
S1=0
S0=M
CENTER
(%)
+/–1.2
+/–1.1
+/–0.9
+/–0.9
+/–1.2
+/–1.1
+/–0.9
+/–0.9
+/–1.2
+/–1.1
+/–0.9
+/–0.9
S1=0
S0=1
CENTER
(%)
+/–0.6
+/–0.5
+/–0.5
+/–0.4
+/–0.6
+/–0.5
+/–0.5
+/–0.4
+/–0.6
+/–0.5
+/–0.5
+/–0.4
S1=M
S0=0
CENTER
(%)
+/–0.5
+/–0.4
+/–0.4
+/–0.3
+/–0.5
+/–0.4
+/–0.4
+/–0.3
+/–0.5
+/–0.4
+/–0.4
+/–0.3
S1=1
S0=1
DOWN
(%)
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
S1=1
S0=0
DOWN
(%)
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
S1=M
S0=1
DOWN
(%)
–1.9
–.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
S1=1
S0=M
DOWN
(%)
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
S1=M
S0=M
NO
SPREAD
0
0
0
0
0
0
0
0
0
0
0
0
3-Level Digital Inputs
Figure 2. 3-Level Logic
LOGIC
LOW (0)
LOGIC
MIDDLE (M)
LOGIC
HIGH (H)
VDD
DO, D1, S0, S1
and
FRSEL
to GND
D0, D1, S0, S1
and
FRSEL
UNCONNECTED
D0, D1, S0, S1
and
FRSEL
to VDD
GND
S0, S1, D0, D1, and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High - 1,
Low- 0 and Middle- M. With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0,
S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL.
S0, S1, D0, D1, and FRSEL pins include an on chip 20K (10K /10K) resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown in the following:
Logic State 0 = 3-Level logic pin connected to GND.
Logic State M = 3-Level logic pin left floating (no connection).
Logic State 1 = 3-Level logic pin connected to VDD.
Figure 2 illustrates how to implement 3-Level Logic.
Document Number: 38-07111 Rev. *D
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