CY2308_12 Datasheet, PDF (6/18 Pages) Cypress Semiconductor – 3.3 V Zero Delay Buffer

CY2308
Switching Characteristics for Commercial Temperature Devices
Parameter ^[9]
Name
Test Conditions
Min Typ
Max
Unit
F_in
Input frequency
–
t₁
Output frequency
30 pF load
10 –
133.3
MHz
10 – 100 (-1, -2, -3, -4) MHz
66.67 (-5H)
t₁
Output frequency
20 pF load, -1H, -5H devices
10 –
133.3 (-1H) MHz
66.67 (-5H)
t₁
Output frequency
15 pF load, -1, -2, -3, -4 devices
10 –
133.3
MHz
t_PD
Duty cycle ^[9] = t₂ t₁
Measured at 1.4 V, F_OUT = 66.66 MHz, 30 pF load 40.0 50.0
60.0
%
(-1, -2, -3, -4, -1H, -5H)
t_PD
Duty cycle ^[9] = t₂ t₁
Measured at 1.4 V, F_OUT < 50 MHz, 15 pF load 45.0 50.0
55.0
%
(-1, -2, -3, -4, -1H, -5H)
t₃
Rise time ^[9] (-1, -2, -3, -4) ^{Measured between 0.8 V and 2.0 V, 30 pF load – –}
2.20
ns
t₃
Rise time ^[9] (-1, -2, -3, -4) ^{Measured between 0.8 V and 2.0 V, 15 pF load – –}
1.50
ns
t₃
Rise time ^[9] (-1H, -5H)
Measured between 0.8 V and 2.0 V, 30 pF load – –
1.50
ns
t₄
Fall time ^[9] (-1, -2, -3, -4) ^{Measured between 0.8 V and 2.0 V, 30 pF load – –}
2.20
ns
t₄
Fall time ^[9] (-1, -2, -3, -4) ^{Measured between 0.8 V and 2.0 V, 15 pF load – –}
1.50
ns
t₄
Fall time ^[9] (-1H, -5H)
Measured between 0.8 V and 2.0 V, 30 pF load – –
1.25
ns
t₅
Output to output skew on All outputs equally loaded
same Bank ^[9] (-1, -2, -3, -4)
––
200
ps
Output to output skew (-1H, All outputs equally loaded
-5H)
––
200
ps
Output Bank A to output Bank All outputs equally loaded
B skew (-1, -4, -5H)
––
200
ps
Output Bank A to output Bank All outputs equally loaded
B skew (-2, -3)
––
400
ps
t₆
Delay, REF rising edge to
FBK rising edge ^[9]
Measured at V_DD/2
–0
±250
ps
t₇
Device to device skew ^[9]
Measured at V_DD/2 on the FBK pins of devices – 0
700
ps
t₈
Output slew rate ^[9]
Measured between 0.8 V and 2.0 V on -1H, -5H 1 –
–
V/ns
device using Test Circuit 2
t_J
Cycle to cycle Jitter ^[9] (-1, ^{Measured at 66.67 MHz, loaded outputs, 15 pF – 75}
200
ps
-1H, -4, -5H)
load
Measured at 66.67 MHz, loaded outputs, 30 pF – –
200
ps
load
Measured at 133.3 MHz, loaded outputs, 15 pF – –
100
ps
load
t_J
Cycle to cycle Jitter ^[9] (-2, -3) ^{Measured at 66.67 MHz, loaded outputs, 30 pF – –}
400
ps
load
t_LOCK
PLL lock time ^[9]
Measured at 66.67 MHz, loaded outputs, 15 pF – –
load
Stable power supply, valid clocks presented on – –
REF and FBK pins
400
ps
1.0
ms
Note
9. All parameters are specified with loaded outputs.
Document Number: 38-07146 Rev. *M
Page 6 of 18
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