CY14B104NA-ZS25XI Datasheet, PDF (6/26 Pages) Cypress Semiconductor – 4-Mbit (512 K x 8/256 K x 16) nvSRAM

CY14B104LA, CY14B104NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t_DELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104LA/CY14B104NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B104LA/CY14B104NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for t_LZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(V_CC< V_SWITCH), an internal RECALL request is latched. When
V_CC again exceeds the V_SWITCH on power up, a RECALL cycle
is automatically initiated and takes t_HRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by
a
software
address
sequence.
The
CY14B104LA/CY14B104NA software STORE cycle is initiated
by executing sequential CE or OE controlled read cycles from six
specific address locations in exact order. During the STORE
cycle an erase of the previous non-volatile data is first performed,
followed by a program of the non-volatile elements. After a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
Table 1. Mode Selection
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t_STORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the t_RECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
CE
WE
OE
BHE, BLE^{[11] A}15^–A0^[12]
Mode
I/O
Power
H
X
X
X
X
Not selected Output high Z
Standby
L
H
L
L
X
Read SRAM Output data
Active
L
L
X
L
X
Write SRAM
Input data
Active
L
H
L
X
0x4E38
Read SRAM Output data
Active^[13]
0xB1C7
Read SRAM Output data
0x83E0
Read SRAM Output data
0x7C1F
Read SRAM Output data
0x703F
Read SRAM Output data
0x8B45
AutoStore
Output data
Disable
Notes
11. BHE and BLE are applicable for × 16 configuration only.
12.
While there are 19 address lines
The remaining address lines are
on the CY14B104LA
don’t care.
(18
address
lines
on
the
CY14B104NA),
only
13
address
lines
(A₁₄–A₂)
are
used
to
control
software
modes.
13. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document Number: 001-49918 Rev. *M
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