CY14B101LA_12 Datasheet, PDF (6/29 Pages) Cypress Semiconductor – 1-Mbit (128 K × 8/64 K × 16) nvSRAM

CY14B101LA
CY14B101NA
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See the Truth Table For SRAM Operations on page
18 for a complete description of read and write modes.
SRAM Read
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A_0–16 or A_0–15 determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t_AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t_ACE or at t_DOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t_AA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ_0–15
are written into the memory if the data is valid t_SD before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers t_HZWE after WE goes LOW.
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the
CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from V_CC to
charge a capacitor connected to the V_CAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V_CC pin drops below V_SWITCH, the part
automatically disconnects the V_CAP pin from V_CC. A STORE
operation is initiated with power provided by the V_CAP capacitor.
Note
14. HSB pin is not available in 44-pin TSOP II (× 16) package.
Note If the capacitor is not connected to V_CAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on V_CAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the store. This
corrupts the data stored in nvSRAM.
Figure 4 shows the proper connection of the storage capacitor
(V_CAP) for automatic STORE operation. See the DC Electrical
Characteristics on page 9 for the size of V_CAP. The voltage on
the V_CAP pin is driven to V_CC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
V_CC
0.1 uF
V_CC
WE
V_CAP
V_SS
V_CAP
Hardware STORE Operation
The CY14B101LA/CY14B101NA provides the HSB^[14] pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
initiates a STORE operation after t_DELAY. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t_HHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Document Number: 001-42879 Rev. *O
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