CYRF69313_13 Datasheet, PDF (51/81 Pages) Cypress Semiconductor – Programmable Radio-on-Chip LPstar

CYRF69313
Figure 16. Interrupt Controller Block Diagram
InterruptTaken
or
INT_CLRxWrite
Posted
Interrupt
Pending
Interrupt
Priority
Encoder
Interrupt Vector
Interrupt
Request
R
1
DQ
M8C Core
Interrupt
Source
(Timer,
GPIO,etc.)
INT_MSKx
Mask Bit Setting
CPU_F[0]
GIE
Interrupt Processing
The sequence of events that occur during interrupt processing is
as follows:
1. An interrupt becomes active, either because:
❐ The interrupt condition occurs (for example, a timer expires).
❐ A previously posted interrupt is enabled through an update
of an interrupt mask register.
❐ An interrupt is pending and GIE is set from 0 to 1 in the CPU
Flag register.
❐ The GPIO interrupts are edge triggered.
2. The current executing instruction finishes.
3. The internal interrupt is dispatched, taking 13 cycles. During
this time, the following actions occur:
❐ The MSB and LSB of Program Counter and Flag registers
(CPU_PC and CPU_F) are stored onto the program stack by
an automatic CALL instruction (13 cycles) generated during
the interrupt acknowledge process.
❐ The PCH, PCL, and Flag register (CPU_F) are stored onto
the program stack (in that order) by an automatic CALL
instruction (13 cycles) generated during the interrupt
acknowledge process.
❐ The CPU_F register is then cleared. Because this clears the
GIE bit to 0, additional interrupts are temporarily disabled
❐ The PCH (PC[15:8]) is cleared to zero.
❐ The interrupt vector is read from the interrupt controller and
its value placed into PCL (PC[7:0]). This sets the program
counter to point to the appropriate address in the interrupt
table (for example, 0004h for the POR interrupt).
4. Program execution vectors to the interrupt table. Typically, a
LJMP instruction in the interrupt table sends execution to the
user's Interrupt Service Routine (ISR) for this interrupt.
5. The ISR executes. Note that interrupts are disabled because
GIE = 0. In the ISR, interrupts can be re-enabled if desired by
setting GIE = 1 (care must be taken to avoid stack overflow).
6. The ISR ends with a RETI instruction which restores the
Program Counter and Flag registers (CPU_PC and CPU_F).
The restored Flag register re-enables interrupts, because
GIE = 1 again.
7. Execution resumes at the next instruction, after the one that
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts are processed
before the next normal program instruction.
Interrupt Latency
The time between the assertion of an enabled interrupt and the
start of its ISR can be calculated from the following equation.
Latency = Time for current instruction to finish + Time for internal
interrupt routine to execute + Time for LJMP instruction in
interrupt table to execute.
For example, if the 5 cycle JMP instruction is executing when an
interrupt becomes active, the total number of CPU clock cycles
before the ISR begins would be as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine)
+ (7 cycles for LJMP) = 21 to 25 cycles.
In the example above, at 24 MHz, 25 clock cycles take 1.042 s.
Interrupt Registers
The Interrupt Registers are discussed it the following sections.
Interrupt Clear Register
The Interrupt Clear Registers (INT_CLRx) are used to enable the
individual interrupt sources’ ability to clear posted interrupts.
When an INT_CLRx register is read, any bits that are set
indicates an interrupt has been posted for that hardware
resource. Therefore, reading these registers gives the user the
ability to determine all posted interrupts.
Document Number: 001-66503 Rev. *D
Page 51 of 81