W42C31-06 Datasheet, PDF (5/6 Pages) Cypress Semiconductor – Spread Spectrum Frequency Timing Generator

W42C31-06
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
V_DD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V_DD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V_DD connection can be
made via a ferrite bead, as shown.
The 6-pF XTAL load capacitors can be used to raise the inte-
grated 17-pF capacitance up to a total load of 20 pF on the
crystal.
Recommended Board Layout
Figure 5 shows a recommended 2-layer board layout.
C1
6 pF
C2
6 pF
XTAL1
1
2
GND
3
4
8
7
6
V_DD
5
R1
Output
C3
0.1 µF
5V System Supply
FB
Figure 4. Recommended Circuit Configuration
C4
10 µF Tantalum
Optional Guard Ring for
XTAL Oscillator Circuitry
G
C1
G
XTAL1
C2
G
G
Power Supply Input
(5V)
FB
C1, C2 =
C3 =
C4 =
R1 =
XTAL load capacitors (optional; use
is not required for operation).
Typical value is 6 pF.
High frequency supply decoupling
capacitor (0.1-µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
Match value to line impedance
FB = Ferrite Bead
G = Via To GND Plane
C3
G
R1
C4
G
Clock Output
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
Freq. Mask
Code
W42C31
06
Document #: 38-00800
Package
Name
G
Package Type
8-pin Plastic SOIC (150-mil)
5