|
W40S11-23 Datasheet, PDF (5/9 Pages) Cypress Semiconductor – Clock Buffer/Driver | |||
|
◁ |
W40S11-23
Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a âstart bitâ as shown in Figure
3. A âstop bitâ signifies that a transmission has ended.
As stated previously, the W40S11-23 sends an âacknowledgeâ
pulse after receiving eight data bits in each byte as shown in
Figure 4.
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Stop
Bit
Figure 3. Serial Data Bus Start and Stop Bit
5
|
▷ |