W170-01G Datasheet, PDF (5/6 Pages) Cypress Semiconductor – Spread Aware, Frequency Multiplier and Zero Delay Buffer

W170-01
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V±5%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
f_IN
Input Frequency^[1]
OUT2 = REF
MHz
f_OUT
Output Frequency
OUT1
20
133
MHz
t_R
Output Rise Time
0.8V to 2.0V, 15-pF load
3.5
ns
t_F
t_ICLKR
t_ICLKF
t_PD
Output Fall Time
Input Clock Rise Time^[2]
Input Clock Fall Time^[2]
FBIN to IN (Reference Input) Skew^{[3, 4]}
2.0V to 0.8V, 15-pF load
Note 4
2.5
ns
10
ns
10
ns
300
ps
t_D
Duty Cycle
Note 5
40
50
60
%
t_LOCK
PLL Lock Time
Power supply stable
1.0
ms
t_JC
Jitter, Cycle-to-Cycle
Note 6
200
ps
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 5V±10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
f_IN
Input Frequency^[1]
OUT2 = REF
MHz
f_OUT
Output Frequency
OUT1
20
133
MHz
t_R
Output Rise Time
0.8V to 2.0V, 15-pF load
3.5
ns
t_F
t_ICLKR
t_ICLKF
t_PD
Output Fall Time
Input Clock Rise Time^[2]
Input Clock Fall Time^[2]
FBIN to IN (Reference Input) Skew^{[3, 4]}
2.0V to 0.8V, 15-pF load
Note 4
2.5
ns
10
ns
10
ns
300
ps
t_D
Duty Cycle
Note 7, 8
40
50
60
%
t_LOCK
PLL Lock Time
Power supply stable
1.0
ms
t_JC
Jitter, Cycle-to-Cycle
Note 6
200
ps
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. Longer input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4. Skew is measured at 1.4V on rising edges.
5. Duty cycle is measured at 1.4V.
6. Jitter is measured on 133-MHz signal at 1.4V.
7. Duty cycle is measured at 1.4V, 120 MHz.
8. Duty cycle at 133 MHz is 35/65 worst case.
Ordering Information
Ordering Code
W170
Document #: 38-00795
Option
-01
Package
Name
G
Package Type
8-pin SOIC (150 mil)
5