CYV15G0204RB_09 Datasheet, PDF (5/24 Pages) Cypress Semiconductor – Independent Clock Dual HOTLink II Reclocking Deserializer

CYV15G0204RB
Pin Configuration (Top View)^[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
NC
NC
NC
NC
V_CC
IN
B1–
ROUT _GND
B1–
IN
B2–
ROUT
B2–
IN
A1–
ROUT _GND
A1–
IN
A2–
ROUT
A2–
V_CC
V_CC
NC V_CC NC
B
V_CC
NC
V_CC
NC
V_CC
IN
B1+
ROUT _GND
B1+
IN
B2+
ROUT
B2+
IN
A1+
ROUT _GND
A1+
IN
A2+
ROUT
A2+
V_CC
NC
NC
NC
NC
C
TDI
TMS
V_CC
V_CC
V_CC ^ULCB
NC
GND ^{DATA DATA DATA DATA} GND
[6]
[4]
[2]
[0]
NC
SPD
SELB
V_CC
LDTD TRST _GND
EN
TDO
D
TCLK RESET INSELB INSELA _VCC ULCA
NC
GND ^{DATA DATA DATA} GND GND GND
[5]
[3]
[1]
NC
V_CC
NC
V_CC
SCAN TMEN3
EN2
E
V_CC V_CC V_CC V_CC
V_CC V_CC V_CC V_CC
F
NC NC V_CC V_CC
V_CC NC NC NC
G
GND ^WREN GND GND
H
GND GND GND GND
NC NC ^SPD NC
SELA
GND GND GND GND
J
GND GND GND GND
NC NC NC NC
K
NC NC GND GND
NC NC NC NC
L
NC NC NC GND
NC NC NC GND
M
NC NC NC NC
NC NC NC GND
N
GND GND GND GND
GND GND GND GND
P
NC NC NC NC
GND GND GND GND
R
NC NC NC NC
V_CC V_CC V_CC V_CC
T
V_CC V_CC V_CC V_CC
V_CC V_CC V_CC V_CC
U
V_CC
V_CC
V_CC
V_CC
V_CC
RX
DB[4]
RX
DB[3]
GND GND ^{ADDR TRG} GND GND GND
[0] CLKB–
V_CC
V_CC
RX
DA[4]
V_CC
BIST RX
STA DA[0]
V
V_CC
V_CC
V_CC
RX
DB[8]
V_CC
RX
DB[5]
RX
DB[1]
GND
BIST
STB
GND ^{TRG RE} GND GND
CLKB+ CLKOA
V_CC
V_CC
RX
RX
RX
RX
DA[9] DA[5] DA[2] DA[1]
W
V_CC
V_CC
LFIB
RX
CLKB–
V_CC
RX
DB[6]
RX
DB[0]
GND ^{ADDR ADDR RX}
RE _{GND GND}
[2]
[1] CLKA+ PDOA
V_CC
V_CC
LFIA TRG RX
RX
CLKA+ DA[6] DA[3]
Y
V_CC
V_CC
RX
DB[9]
RX
CLKB+
V_CC
RX RX _GND RE _NC
DB[7] DB[2]
CLKOB
GND ^RX GND GND
CLKA–
V_CC
V_CC
RE TRG RX
PDOB CLKA– DA[8]
RX
DA[7]
Note
1. NC = Do not connect.
Document #: 38-02103 Rev. *C
Page 5 of 24
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