CYK128K16MCCB Datasheet, PDF (5/9 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Pseudo Static RAM

Switching Characteristics Over the Operating Range (continued)^[10]
55 ns^[14]
Parameter
Description
Min.
Max.
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z^{[11, 13]}
WE HIGH to Low-Z^{[11, 13]}
50
25
0
25
5
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)^{[15, 16, 17]}
t_RC
ADDRESS
DATA OUT
t_SK
t_OHA
t_AA
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)^{[16, 17]}
CYK128K16MCCB
70 ns
Min.
Max.
Unit
60
ns
45
ns
0
ns
25
ns
5
ns
DATA VALID
ADDRESS
CE
t_SK
t_RC
BHE/BLE
t_ACE
OE
DATA OUT
VCC
SUPPLY
CURRENT
t_LZBE
t_DBE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
50%
t_HZCE
t_HZBE
t_HZOE
DATA VALID
50%
HIGH
IMPEDANCE
I_CC
I_SB
Notes:
15. Device is continuously selected. OE, CE = V_IL.
16. WE is HIGH for Read Cycle.
17. For the 55-ns Cycle, the addresses must not toggle once the read is started on the device. For the 70-ns Cycle, the addresses must be stable within 10 ns after
the start of the read cycle.
Document #: 38-05584 Rev. *C
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