CY7C67200_11 Datasheet, PDF (5/78 Pages) Cypress Semiconductor – EZ-OTG Programmable USB On-The-Go Package option: 48-pin FBGA

CY7C67200
Host Port Interface (HPI)
EZ-OTG has an HPI interface. The HPI interface provides
DMA access to the EZ-OTG internal memory by an external
host, plus a bidirectional mailbox register for supporting
high-level communication protocols. This port is designed to
be the primary high-speed connection to a host processor.
Complete control of EZ-OTG can be accomplished through
this interface via an extensible API and communication
protocol. Other than the hardware communication protocols, a
host processor has identical control over EZ-Host whether
connecting to the HPI or HSS port. The HPI interface is
exposed through GPIO pins.
Note It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as
outputs for a test mode. If these pins need to be used as inputs,
a series resistor is required (10 ohm to 48 ohm is recom-
mended). Refer to BIOS documentation for addition details.
See section “Reset Pin” on page 9.
HPI Features
• 16-bit data bus interface
• 16 MB/s throughput
• Auto-increment of address pointer for fast block mode
transfers
• Direct memory access (DMA) to internal memory
• Bidirectional Mailbox register
• Byte Swapping
• Complete access to internal memory
• Complete control of SIEs through HPI
• Dedicated HPI Status register
HPI Pins
Table 9. HPI Interface Pins ^{[1, 2]}
INT
nRD
nWR
nCS
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
Pin Name
Pin Number
H4
G4
H5
G5
H6
F5
F6
E4
E5
E6
D4
D5
C6
C5
Table 9. HPI Interface Pins ^{[1, 2]} (continued)
Pin Name
D7
D6
D5
D4
D3
D2
D1
D0
Pin Number
B5
B4
C4
B3
A3
C3
A2
B2
The two HPI address pins are used to address one of four
possible HPI port registers as shown in Table 10 below.
Table 10.HPI Addressing
HPI A[1:0]
HPI Data
HPI Mailbox
HPI Address
HPI Status
A1
A0
0
0
0
1
1
0
1
1
Charge Pump Interface
VBUS for the USB On-The-Go (OTG) port can be produced by
EZ-OTG using its built-in charge pump and some external
components. The circuit connections should look similar to
Figure 1 below.
Figure 1. Charge Pump
CSWITCHA
CY7C67200
CSWITCHB
OTGVBUS
D1
D2
C1
VBUS
C2
Component details:
• D1 and D2: Schottky diodes with a current rating greater
than 60 mA.
• C1: Ceramic capacitor with a capacitance of 0.1 µF.
• C2: Capacitor value must be no more that 6.5 µF since that
is the maximum capacitance allowed by the USB OTG
specification for a dual-role device. The minimum value of
C2 is 1 µF. There are no restrictions on the type of capacitor
for C2.
If the VBUS charge pump circuit is not to be used,
CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon-
nected.
Notes
1. HPI_INT is for the Outgoing Mailbox Interrupt.
2. HPI strobes are negative logic sampled on rising edge.
Document #: 38-08014 Rev. *G
Page 5 of 78
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