CY7C4281_05 Datasheet, PDF (5/16 Pages) Cypress Semiconductor – 64K/128K x 9 Deep Sync FIFOs

CY7C4281
CY7C4291
RESET (RS)
DATA IN (D) _{18 9}
WRITECLOCK (WCLK)
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAF)
CY7C4281/91
FULL FLAG (FF) # 1
FF
EF
FULL FLAG (FF) # 2
9
Read Enable 2 (REN2)
RESET (RS)
9
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
CY7C4281/91
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
FF
EF
9 ^{DATA OUT (Q)} 18
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration
Document #: 38-06007 Rev. *C
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