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| CY7C372I-66YMB Datasheet, PDF (5/13 Pages) Cypress Semiconductor – UltraLogic 64-Macrocell Flash CPLD | |||
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CY7C372i
Capacitance[9]
Parameter
CI/O[11, 12]
CCLK
Description
Input Capacitance
Clock Signal Capacitance
Test Conditions
VIN = 5.0V at f = 1 MHz
VIN = 5.0V at f = 1 MHz
Min.
5
Inductance[9]
Parameter
L
Description
Test Conditions
Maximum Pin Inductance VIN = 5.0V at f = 1 MHz
44-Lead CLCC
2
Endurance Characteristics[9]
Parameter
Description
N
Maximum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
AC Test Loads and Waveforms
238⦠(com'l)
319⦠(mil)
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
(a)
170⦠(com'l)
236⦠(mil)
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
238⦠(com'l)
319⦠(mil)
170⦠(com'l)
236⦠(mil)
(b)
Equivalent to: THÃVENIN EQUIVALENT
OUTPUT
99⦠(com'l)
136⦠(mil) 2.08V(com'l)
2.13V(mil)
3.0V
GND
< 2 ns
ALL INPUT PULSES
90%
10%
(c)
Max.
Unit
8
pF
12
pF
44-Lead PLCC Unit
5
nH
Max.
100
Unit
Cycles
90%
10%
< 2 ns
Parameter[13]
tER(â)
Vx
1.5V
Output Waveform Measurement Level
V OH
0.5V
VX
tER(+)
2.6V
V OL
0.5V
VX
tEA(+)
1.5V
0.5V
VX
tEA(â)
Vthe
VX
0.5V
(d) Test Waveforms
Note:
11. CI/O for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max.
12. CI/O for CLCC package is 15 pF Max.
13. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
V OH
V OL
Document #: 38-03033 Rev. *A
Page 5 of 13
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