CY7C346 Datasheet, PDF (5/21 Pages) Cypress Semiconductor – USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)

USE ULTRA37000^TM FOR
ALL NEW DESIGNS
CY7C346
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
The CY7C346 is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Typical I_CC vs. f_MAX
400
300
V_CC = 5.0V
Room Temp.
200
100
0
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
Output Drive Current
100
I_OL
80
V_CC = 5.0V
60
Room Temp.
40
I_OH
20
0 ^0.45 1
2
3
4
5
V_O OUTPUT VOLTAGE (V)
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t_EXP to the overall delay. Similarly, there is an
additional t_PIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use t_S1 if all
inputs are on dedicated input pins. The parameter t_S2 should
be used if data is applied at an I/O pin. If t_S2 is greater than
t_CO1, 1/t_S2 becomes the limiting frequency in the data path
mode unless 1/(t_WH + t_WL) is less than 1/t_S2.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t_EXP to t_S1. Determine which
of 1/(t_WH + t_WL), 1/t_CO1, or 1/(t_EXP + t_S1) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use
t_AS1 if all inputs are on the dedicated input pins. If any data
is applied to an I/O pin, t_AS2 must be used as the required
set-up time. If (t_AS2 + t_AH) is greater than t_ACO1, 1/(t_AS2 + t_AH)
becomes the limiting frequency in the data path mode unless
1/(t_AWH + t_AWL) is less than 1/(t_AS2 + t_AH).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t_EXP to t_AS1. Determine
which of 1/(t_AWH + t_AWL), 1/t_ACO1, or 1/(t_EXP + t_AS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
The parameter t_OH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If t_OH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
The parameter t_AOH indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same asynchronous clock
as the CY7C346.
In general, if t_AOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous) then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same.
This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This
is due to the expander logic in the second device’s clock
signal path adding an additional delay (t_EXP) causing the
output data from the preceding device to change prior to the
arrival of the clock signal at the following device’s register.
Document #: 38-03005 Rev. *B
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