CY7C1345G_07 Datasheet, PDF (5/20 Pages) Cypress Semiconductor – 4-Mbit (128K x 36) Flow Through Sync SRAM

CY7C1345G
Pin Definitions
Name
IO
Description
A0, A1, A
Input
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃ are sampled active. A_[1:0] feed
the two-bit counter.
BW_A, BW_B
BW_C, BW_D
GW
BWE
Input
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW_[A:D] and BWE).
Input
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
Synchronous LOW to conduct a byte write.
CLK
Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE₁
Input
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE₂ and CE₃ to select or deselect the device. ADSP is ignored if CE₁ is HIGH. CE₁ is sampled only
when a new external address is loaded.
CE₂
Input
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE₁ and CE₃ to select or deselect the device. CE₂ is sampled only when a new external address is
loaded.
CE₃
Input
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE₁ and CE₂ to select or deselect the device. CE₃ is sampled only when a new external address is
loaded.
OE
Input
Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When
Asynchronous LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
ADSP
ADSC
Input
Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A_[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE₁ is deasserted HIGH.
Input
Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A_[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized.
ZZ
Input
ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
has an internal pull down.
DQs
DQP_A, DQP_B
DQP_C, DQP_D
V_DD
V_SS
V_DDQ
IO
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the pins
is controlled by _OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and
DQP_[A:D] are placed in a tri-state condition.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
IO Power Power supply for the IO circuitry.
Supply
V_SSQ
IO Ground Ground for the IO circuitry.
Document Number: 38-05517 Rev. *E
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