CY62167EV18_11 Datasheet, PDF (5/16 Pages) Cypress Semiconductor – 16 Mbit (1M x 16) Static RAM Automatic power down when deselected

CY62167EV18 MoBL^®
Thermal Resistance
Parameter^[11]
Description
_JA
Thermal resistance
(Junction to ambient)
_JC
Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
VFBGA
(6 × 8 × 1mm)
55
16
Unit
C/W
C/W
Figure 2. AC Test Loads and Waveforms
R1
V_CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
V_CC
10% ^90%
90%
10%
R2
GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
R_TH
V
Parameters
1.8 V
Unit
R1
13500

R2
10800

R_TH
6000

V_TH
0.80
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ^[12] Max Unit
V_DR
V_CC for data retention
1.0
–
I_CCDR[13]
Data retention current V_CC = 1.0 V, CE₁ > V_CC – 0.2 V or CE₂ < 0.2 V or (BHE
–
–
and BLE) > V_CC – 0.2 V, V_IN > V_CC – 0.2 V or V_IN < 0.2 V
t_CDR[11]
Chip deselect to data
retention time
0
–
t_R[14]
Operation recovery time
55
–
–
V
10
A
–
ns
–
ns
Figure 3. Data Retention Waveform
V_CC
CE₁ or
[15]
BHE.BLE
or
CE₂
V_CC(min)
t_CDR
DATA RETENTION MODE
V_DR > 1.0 V
V_CC(min)
t_R
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V_CC = V_CC(typ), T_A = 25 °C.
13. Chip enables (CE₁ and CE₂), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the I_SB1 /I_SB2 / I_CCDR spec. Other inputs can be left floating.
14. Full device operation requires linear V_CC ramp from V_DR to V_CC(min) > 100 s or stable at V_CC(min) > 100 s.
15. BHE. BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05447 Rev. *L
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