CY62128EV30_11 Datasheet, PDF (5/15 Pages) Cypress Semiconductor – 1-Mbit (128 K × 8) Static RAM Typical standby current: 1 μA

CY62128EV30 MoBL^®
Capacitance
Parameter^[9]
Description
C_IN
Input capacitance
C_OUT
Output capacitance
Thermal Resistance
Parameter^[9]
Description
_JA
Thermal resistance
(junction to ambient)
_JC
Thermal resistance
(junction to case)
Test Conditions
T_A = 25 °C, f = 1 MHz,
V_CC = V_CC(typ)
Test Conditions
Still air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
Max
10
10
TSOP I
33.01
3.42
SOIC
48.67
25.86
Unit
pF
pF
STSOP
32.56
3.59
Unit
°C/W
°C/W
R1
V_CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Figure 4. AC Test Loads and Waveforms
ALL INPUT PULSES
R2
V_CC
GND
10%
90%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
R_TH
V
Parameters
R1
R2
R_TH
V_TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
V_DR
I_CCDR^[11]
t_CDR^[9]
t_R^[12]
V_CC for data retention
Data retention current
V_CC = 1.5 V,
CE₁ > V_CC 0.2 V or CE₂ < 0.2 V,
V_IN > V_CC 0.2 V or V_IN < 0.2 V
Chip deselect to data retention time
Operation recovery time
Industrial
Unit



V
Min Typ^[10] Max Unit
1.5
–
–V
–
–
3 µA
0
–
– ns
45
–
– ns
Note
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V_CC = V_CC(typ), T_A = 25 °C.
11. Chip enables (CE₁ and CE₂) must be at CMOS level to meet the I_SB2 / I_CCDR spec. Other inputs can be left floating.
12. Full device AC operation requires linear V_CC ramp from V_DR to V_CC(min) > 100 µs or stable at V_CC(min)  100 µs.
Document #: 38-05579 Rev. *I
Page 5 of 15
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