CY62128BN Datasheet, PDF (5/12 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM

CY62128BN
MoBL^®
Switching Characteristics^[7] Over the Operating Range
Parameter
Description
READ CYCLE
t_RC
Read Cycle Time
t_AA
Address to Data Valid
t_OHA
Data Hold from Address Change
t_ACE
CE₁ LOW to Data Valid, CE₂ HIGH to Data Valid
t_DOE
OE LOW to Data Valid
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Low Z
OE HIGH to High Z^{[7, 9]}
CE₁ LOW to Low Z, CE₂ HIGH to Low Z^[9]
CE₁ HIGH to High Z, CE₂ LOW to High Z^{[8, 9]}
t_PU
CE₁ LOW to Power-up, CE₂ HIGH to Power-up
t_PD
CE₁ HIGH to Power-down, CE₂ LOW to Power-down
WRITE CYCLE^[10]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_LZWE
t_HZWE
Write Cycle Time
CE₁ LOW to Write End, CE₂ HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z^[9]
WE LOW to High Z^{[8, 9]}
CY62128BN-55 CY62128BN-70
Min. Max. Min. Max. Unit
55
70
ns
55
70
ns
5
5
ns
55
70
ns
20
35
ns
0
0
ns
20
25
ns
5
5
ns
20
25
ns
0
0
ns
55
70
ns
55
70
ns
45
60
ns
45
60
ns
0
0
ns
0
0
ns
45
50
ns
25
30
ns
0
0
ns
5
5
ns
20
25
ns
Switching Waveforms
Read Cycle No.1^{[11, 12]}
ADDRESS
DATA OUT
t_RC
t_AA
t_OHA
PREVIOUS DATA VALID
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 100-pF load capacitance.
8. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE₁ LOW, CE₂ HIGH, and WE LOW. CE₁ and WE must be LOW and CE₂ HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE₁ = V_IL, CE₂ = V_IH.
12. WE is HIGH for read cycle.
Document #: 001-06498 Rev. *A
Page 5 of 12
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