CY62127DV20 Datasheet, PDF (5/12 Pages) Cypress Semiconductor – 1M (64K x 16) Static RAM

ADVANCE
INFORMATION
CY62127DV20
MoBL2^®
AC Test Loads and Waveforms
R1
V_CC
UTPUT
C_L = 30 pF
INCLUDING
JIG AND
SCOPE
V_CC Typ
10%
GND
R2
Rise Time:
1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
R_TH
V
ALL INPUT PULSES
90%
90%
10%
Fall Time:
1 V/ns
Parameters
R1
R2
R_TH
V_{T H}
1.8V
1350 0
1080 0
6000
0.80
UNIT
Ω
Ω
Ω
V
Data Retention Characteristics
Parameter
V_DR
I_CCDR
t_CDR[5]
t_R[6]
Description
Conditions
V_CC for Data Retention
Data Retention Current
V_CC = 1V, CE₁ > V_CC − 0.2V, CE₂ < L
0.2V, V_IN > V_CC − 0.2V or V_IN < 0.2V _LL
Chip Deselect to Data Reten-
tion Time
Operation Recovery Time
Min.
1
0
t_RC
Typ.^[4]
Max.
2.2
1
TBD
Unit
V
µA
ns
ns
Data Retention Waveform^[7]
V_CC
CE₁ or
BHE ^.BLE
or
CE₂
V_CC(min.)
t_CDR
DATA RETENTION MODE
V_DR > 1.0V
V_CC(min.)
t_R
Notes:
6.
7.
Full device operation
BHE^.BLE is the AND
requires linear V_CC ramp from V_DR
of both BHE and BLE. Chip can be
to V_CC(min.)
deselected
> 100 µs
by either
or stable
disabling
at V_CC(min.) > 100 µs.
the chip enable signals
or
by
disabling
both.
Document #: 38-05301 Rev. **
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