CY62126DV30_06 Datasheet, PDF (5/12 Pages) Cypress Semiconductor – 1-Mbit (64K x 16) Static RAM

Switching Characteristics (Over the Operating Range)^[10]
Parameter
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
Write Cycle^[13]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z^[11]
OE HIGH to High Z^{[11, 12]}
CE LOW to Low Z^[11]
CE HIGH to High Z^{[11, 12]}
CE LOW to Power-up
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z^[11]
BLE/BHE HIGH to High-Z^{[11, 12]}
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z^{[11, 12]}
WE HIGH to Low Z^[11]
CY62126DV30 MoBL^®
CY62126DV30-55
Min.
Max.
Unit
55
ns
55
ns
10
ns
55
ns
25
ns
5
ns
20
ns
10
ns
20
ns
0
ns
55
ns
25
ns
5
ns
20
ns
55
ns
40
ns
40
ns
0
ns
0
ns
40
ns
40
ns
25
ns
0
ns
20
ns
10
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V_CC(typ.)/2, input pulse levels of 0 to V_CC(typ.), and output loading of
the specified I_OL.
11. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZBE is less than t_LZBE, t_HZOE is less than t_LZOE.
12. t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high-impedance state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = V_IL, BHE and/or BLE = V_IL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05230 Rev. *H
Page 5 of 12
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