CY28158 Datasheet, PDF (5/10 Pages) Cypress Semiconductor – Spread Spectrum Timing Solution for Serverworks Chipset

CY28158
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
I_DD3
3.3V Power Supply Cur-
rent
I_DDPD2
I_DDPD3
2.5V Shutdown Current
3.3V Shutdown Current
Test Conditions
V_DDA/V_DD33 = 3.465V, V_DD25 = 2.625V, F_CPU = 133 MHz
V_DDA/V_DD33 = 3.465V, V_DD25 = 2.625V
V_DDA/V_DD33 = 3.465V, V_DD25 = 2.625V
Min. Max. Unit
160 mA
100 µA
200 µA
Switching Characteristics^[5] Over the Operating Range
Parameter
t₁
t₂
Output
All
CPU,
IOAPIC
Description
Output Duty Cycle^[6]
Rising Edge Rate
Test Conditions
t_1A/t_1B
Between 0.4V and 2.0V
Min.
45
1.0
Max.
55
4.0
t₂
48MHZ, REF Rising Edge Rate
Between 0.4V and 2.4V
t₂
PCI, 3V66
Rising Edge Rate
Between 0.4V and 2.4V
t₃
CPU,
Falling Edge Rate
Between 2.0V and 0.4V
IOAPIC
0.5 2.0
1.0 4.0
1.0 4.0
t₃
48MHZ, REF Falling Edge Rate
Between 2.4V and 0.4V
0.5 2.0
t₃
PCI, 3V66
Falling Edge Rate
Between 2.4V and 0.4V
1.0 4.0
t₆
CPU
CPU-CPU Skew
Measured at 1.25V
175
t₈
IOAPIC
IOAPIC-IOAPIC Skew
Measured at 1.25V
250
t₉
3V66
3V66-3V66 Skew
Measured at 1.5V
250
t₁₀
PCI
PCI-PCI Skew
Measured at 1.5V
500
t₁₁
CPU, 3V66
CPU-3V66 Clock Skew
CPU leads. Measured at 1.25V for
0
1.5
2.5V clocks and 1.5V for 3.3V clocks
t₁₂
3V66, PCI
3V66-PCI Clock Skew
3V66 leads. Measured at 1.5V
0.5 2.5
t₁₃
CPU, IOAPIC CPU-IOAPIC Clock Skew CPU leads. Measured at 1.25V
1.5
4
CPU
Cycle-Cycle Clock Jitter With all outputs running
150
IOAPIC
Cycle-Cycle Clock Jitter
500
48MHZ
Cycle-Cycle Clock Jitter
500
3V66
Cycle-Cycle Clock Jitter
500
REF
Cycle-Cycle Clock Jitter
1000
CPU, PCI
Settle Time
CPU and PCI clock stabilization from
3
power-up
Notes:
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. All parameters specified with loaded outputs.
6. Duty cycle is measured at 1.5V when V_DD = 3.3V. When V_DD = 2.5V, duty cycle is measured at 1.25V.
Unit
%
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ms
Document #: 38-07039 Rev. *B
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