CY23FS04_05 Datasheet, PDF (5/12 Pages) Cypress Semiconductor – Failsafe™ 2.5V/ 3.3V Zero Delay Buffer

REF1
REF2
REFSEL
0 ms
CY23FS04
0 deg
-1 8 0 d e g
0 ms
1 .4 m s
Figure 6. Sample Timing of Muxing Between Two Reference Clocks 180°C Out of Phase and
Resulting Output Phase Offset Typical Settling Time (105 MHz)
190 fs/cy
0
0 ms
190 fsec/cycle = 0.125 mradian/cycle
1.4 ms
Figure 7. Resulting Output dphase/Cycle Typical Rate of Change (105 MHz)
Document #: 38-07304 Rev. *C
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