CY2310ANZ Datasheet, PDF (5/15 Pages) Cypress Semiconductor – 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs

CY7C138
CY7C139
Switching Characteristics Over the Operating Range^[8]
7C138-15
7C139-15
Parameter
Description
Min. Max.
READ CYCLE
t_RC
Read Cycle Time
15
t_AA
Address to Data Valid
15
t_OHA
Output Hold From Address Change 3
t_ACE
CE LOW to Data Valid
15
t_DOE
t_{LZOE[9,10,11]}
t_{HZOE[9,10,11]}
t_{LZCE[9,10,11]}
t_{HZCE[9,10,11]}
t_PU[11]
t_PD[11]
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
10
3
10
3
10
0
15
WRITE CYCLE
t_WC
Write Cycle Time
15
t_SCE
CE LOW to Write End
12
t_AW
Address Set-Up to Write End
12
t_HA
Address Hold From Write End
2
t_SA
Address Set-Up to Write Start
0
t_PWE
Write Pulse Width
12
t_SD
Data Set-Up to Write End
10
t_HD
Data Hold From Write End
0
t_HZWE[10,11] R/W LOW to High Z
10
t_LZWE[10,11] R/W HIGH to Low Z
3
t_WDD[12]
Write Pulse to Data Delay
30
t_DDD[12]
Write Data Valid to Read Data Valid
25
BUSY TIMING^[13]
t_BLA
t_BHA
t_BLC
t_BHC
t_PS
t_WB
t_WH
t_BDD[14]
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
5
R/W LOW after BUSY LOW
0
R/W HIGH after BUSY HIGH
13
BUSY HIGH to Data Valid
INTERRUPT TIMING^[13]
15
15
15
15
Note
13
t_INS
INT Set Time
15
t_INR
INT Reset Time
15
7C138-25
7C139-25
Min. Max.
25
25
3
25
15
3
15
3
15
0
25
25
20
20
2
0
20
15
0
15
3
50
30
20
20
20
20
5
0
20
Note
13
25
25
7C138-35
7C139-35
Min. Max.
35
35
3
35
20
3
20
3
20
0
35
35
30
30
2
0
25
15
0
20
3
60
35
20
20
20
20
5
0
30
Note
13
25
25
7C138-55
7C139-55
Min. Max. Unit
55
ns
55 ns
3
ns
55 ns
25 ns
3
ns
25 ns
3
ns
25 ns
0
ns
55 ns
55
ns
40
ns
40
ns
2
ns
0
ns
30
ns
20
ns
0
ns
25 ns
3
ns
70 ns
40 ns
45 ns
40 ns
40 ns
35 ns
5
ns
0
ns
40
ns
Note ns
13
30 ns
30 ns
5