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CY2304_09 Datasheet, PDF (5/9 Pages) Cypress Semiconductor – 3.3V Zero Delay Buffer | |||
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CY2304
Electrical Characteristics for CY2304SI-X Industrial Temperature Devices (continued)
Parameter
Description
Test Conditions
Min
Max
IDD (PD mode) Power Down Supply Current REF = 0 MHz
â
25.0
IDD
Supply Current
Unloaded outputs, 100 MHz, Select inputs
â
45.0
at VDD or GND
Unloaded outputs, 66 MHz REF (â1, â2)
â
35.0
Unloaded outputs, 33 MHz REF (â1, â2)
â
20.0
Switching Characteristics for CY2304SI-X Industrial Temperature Devices
Parameter[5]
Name
Test Conditions
Min Typ.
t1
Output Frequency
30 pF load, All devices
10
t1
Output Frequency
15 pF load, All devices
10
tDC
Duty Cycle[4] = t2 ÷ t1
(â1,â2)
Measured at 1.4V, FOUT = 66.66 MHz,
30 pF load
40.0 50.0
tDC
Duty Cycle[4] = t2 ÷ t1
(â1,â2)
Measured at 1.4V, FOUT < 50 MHz,
15 pF load
45.0 50.0
t3
Rise Time[4]
(â1, â2)
Measured between 0.8V and 2.0V,
30 pF load
â
â
t3
Rise Time[4]
(â1, â2)
Measured between 0.8V and 2.0V,
15 pF load
â
â
t4
Fall Time[4]
(â1, â2)
Measured between 0.8V and 2.0V,
30 pF load
â
â
t4
Fall Time[4]
(â1, â2)
Measured between 0.8V and 2.0V,
15 pF load
â
â
t5
Output-to-Output Skew on All outputs equally loaded
same Bank (â1,â2)[4]
â
â
Output Bank A to Output
Bank B Skew (â1)
All outputs equally loaded
â
â
Output Bank A to Output
Bank B Skew (â2)
All outputs equally loaded
â
â
t6
Skew, REF Rising Edge to Measured at VDD/2
FBK Rising Edge[4]
â
0
t7
Device-to-Device Skew[4] Measured at VDD/2 on the FBK pins of
â
0
devices
tJ
Cycle-to-Cycle Jitter[4]
Measured at 66.67 MHz, loaded outputs,
â
â
(â1)
15 pF load
Measured at 66.67 MHz, loaded outputs,
â
â
30 pF load
Measured at 133.3 MHz, loaded outputs,
â
â
15 pF load
tJ
Cycle-to-Cycle Jitter[4]
Measured at 66.67 MHz, loaded outputs,
â
â
(â2)
30 pF load
Measured at 66.67 MHz, loaded outputs,
â
â
15 pF load
tLOCK
PLL Lock Time[4]
Stable power supply, valid clocks
presented on REF and FBK pins
â
â
Max
100
133.3
60.0
55.0
2.50
1.50
2.50
1.50
200
200
400
±250
500
180
200
100
400
380
1.0
Unit
μA
mA
mA
mA
Unit
MHz
MHz
%
%
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
Document #: 38-07247 Rev. *F
Page 5 of 9
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